Coordinated Resistive Superconducting Fault Current Limiting for Transmission-Line Current Differential Protection

Habib Muhammad Usman, Marif Daula Siddique, Mohammed Madhat Abualnaeem, 

Forsan Hamoud Abdulmola Hassan, Ahmed Ali Elnour Mahmoud, Abdulrahman Al-Hashedi

Department of Electrical Engineering, King Fahd University of Petroleum and Minerals (KFUPM), Dhahran,

Saudi Arabia

1. INTRODUCTION

Transmission-line protection is a primary layer of power-system security because internal faults must be isolated before thermal, electrodynamic, voltage, and stability consequences spread to adjacent equipment. Current differential protection compares synchronized currents entering a defined zone and is therefore inherently selective: the corrected terminal currents nearly cancel during normal loading and external faults, whereas an internal fault produces a nonzero operating current [1]–[3]. Practical performance is governed by both dependability for internal faults and security during through faults, current-transformer (CT) error, waveform distortion, communication delay, and time-synchronization mismatch [4]. High-resistance internal faults are critical because they reduce the differential operating quantity toward the relay boundary, while low-impedance close-in faults can impose severe current stress on CTs and circuit breakers [5].

The protection problem is increasingly important in networks with high short circuit capacity and low equivalent impedance. A low impedance grid can produce severe close in fault currents that increase the duty imposed on circuit breakers and current transformers [6]. At the same time, a high resistance fault can be difficult to detect because the resulting current is small and may not clearly separate from load or restraint quantities [7]. Recent work on renewable and storage connected lines shows that phasor quality and data reliability remain important for differential protection when converter dominated sources are present [8]. Robust communication and cyber physical security are also increasingly relevant because current differential relays depend on remote terminal data [9].

Superconducting fault current limiters introduce negligible impedance in normal operation and rapidly develop limiting impedance after a quench. Resistive SFCLs are particularly suitable for series insertion because the limiting mechanism is direct and scalable through series-parallel module design [10]–[18]. Their behavior depends on the superconducting layer, stabilizer, shunt path, thermal capacity, cooling boundary, and recovery process; consequently, a network-level post-quench resistance must be interpreted as an aggregate modular parameter rather than the resistance of a single coated-conductor tape [19]–[23]. Recent work also shows that shunt resistance and cooling design materially affect limitation and recovery [38],[52].

Series current-limiting devices can change the quantities used by protection functions. Published studies have reported effects on incremental-frequency, distance, overcurrent, and differential protection [24]–[27], [36][37]. The relevant question is therefore not whether an R-SFCL reduces current, but whether its resistance is coordinated with relay pickup and restraint settings. This distinction is especially important in modern networks where converter-interfaced sources, abnormal samples, synchronization error, and communication latency can already challenge conventional differential protection [53]–[59].

The research gap is the limited traceable analysis of how the complete R-SFCL resistance sweep changes the operating margin and maximum detectable fault resistance of a transmission-line current differential relay. Prior studies often emphasize current reduction or report selected operating points, whereas protection engineering requires a transparent mapping among limiter resistance, differential current, restraint current, pickup margin, and sensitivity limit [36][37].

The research contribution is threefold. First, the study provides a reproducible framework connecting R-SFCL electrothermal behavior, aggregate post-quench resistance, synchronized terminal-current phasors, and the two-condition differential trip boundary. Second, it reports the complete 5–100 Ω sweep and uses maximum detectable fault resistance, percentage improvement, and marginal gain as traceable sensitivity indices for ABC, ABG, AB, and AG faults. Third, it identifies where additional R-SFCL resistance ceases to improve sensitivity and separates this protection optimum from the independent objective of fault-current suppression. The remainder of the paper presents the model and assumptions, the deterministic sensitivity search, quantitative robustness considerations, results, comparison with recent intelligent protection methods, limitations, and conclusions.

2. METHODS

1. Research Design and Simulation Workflow

This study uses a deterministic MATLAB/Simulink comparative design. Identical source, line, fault, and relay settings are simulated without and with the R-SFCL so that changes in relay response can be attributed to the limiter. For each fault type and limiter resistance, the fault resistance is increased until one of the trip conditions is no longer satisfied. The highest fault resistance that still produces a trip is recorded as the sensitivity limit. Performance is evaluated using the absolute increase in this limit, percentage gain, marginal gain between successive limiter settings, and the variation observed across the complete resistance sweep.

The workflow contains five stages. The first stage defines the two source transmission network and line parameters. The second stage inserts the R-SFCL as a modular post quench resistance supported by the electrothermal model. The third stage applies ABC, ABG, AB, and AG internal faults while varying fault resistance. The fourth stage extracts fundamental current phasors at both line terminals. The fifth stage evaluates the differential current, restraint current, practical ratio, and trip condition. Figure 1 presents R-SFCL operating diagram. Figure 2 gives the flowchart used to calculate the maximum detectable fault resistance. Figure 3 shows the simulation architecture.

2. R-SFCL Design Principle

The R-SFCL is placed in series near terminal M of the protected line as depicted in Figure 1. Under normal operation, the current remains lower than the temperature dependent critical current and the device has negligible resistance [38]. During a fault, heat generated inside the superconducting element drives a quench and increases the equivalent resistance [39]. After fault clearing, heat exchange with the liquid nitrogen bath supports recovery toward the superconducting state [40]. The model therefore represents the limiter as a low resistance branch before quench and as an aggregate post quench resistance during fault current limitation.

Figure 1. Technical operating cycle of the resistive superconducting fault current limiter used in the protection study

3. Electrical Thermal Model of the R-SFCL

The nonlinear electrical behavior of the superconducting layer is represented using a power law relation, which is commonly used for coated conductor over current analysis [21]. The electric field  in the superconducting layer is

Where  is the critical electric field criterion, J is the current density,  is the temperature dependent critical current density,  is conductor temperature, and n is the power law exponent.

The temperature dependent critical current density is approximated as

Where  is the critical current density at coolant temperature , and  is the critical temperature. This expression captures the reduction of superconducting capability as temperature approaches  [11].

The instantaneous resistance of the superconducting layer is obtained from the field-current relation as

Where  is the active conductor length and  is the equivalent cross sectional area. A metallic shunt or stabilizer layer is included to share current and reduce localized heating, which is consistent with practical R-SFCL designs [41]. The equivalent module resistance is

Where  is the shunt resistance. The network level limiter resistance is

Where  and  are the equivalent numbers of series and parallel modules. Equation (5) justifies the use of 5, 10, 20, 30, 50, and 100 Ω as aggregate R-SFCL values rather than single tape resistance values [14][15].

The investigated 5, 10, 20, 30, 50, and 100 Ω values span three engineering regions: a low-resistance region in which the limiter moderately changes the fault current (5–10 Ω), a coordination region in which relay sensitivity changes rapidly (20–30 Ω), and a high-resistance region used to examine whether further resistance provides additional protection benefit (50–100 Ω). The broad range is consistent with aggregate modular R-SFCL design, while the intermediate values allow the saturation point to be identified from the marginal sensitivity gain [14]–[16],[38].

The lumped thermal balance is written as

Where  is the equivalent thermal capacitance, IHTS is the superconducting layer current, and Rth is the thermal resistance to the coolant. The first term in Equation (6) represents Joule heating, while the second term represents cooling. Thermal electrical analogy models support this type of lumped representation for SFCL transient simulation [20]. Delayed current zeros and current limiting behavior in industrial systems also depend on this electrical thermal interaction [42].

4. Current Differential Relay Model

The current differential relay monitors the terminal currents of the protected line. The instantaneous terminal currents are denoted by  and , with positive polarity into the protected zone. During an internal fault, both terminal currents feed the fault and the algebraic sum becomes non zero. During normal operation or an external through fault, the terminal currents approximately cancel after polarity correction. This principle follows Kirchhoff current law and is the basis of line differential protection [43].

Let  and  denote the fundamental phasors extracted from  and . The differential current is

where  is the relay operating current. The restraint current is defined as

where  represents the through current related restraint quantity. The practical differential-restraint ratio is

where ε is a small positive number used only to avoid division by zero in numerical evaluation.

The relay issues a trip when two conditions are simultaneously satisfied:

In this study, the pickup current is  = 200 A and the restraint coefficient is  = 0.75. The pickup is intentionally well below the smallest reported internal-fault differential operating quantity while remaining above the numerical prefault mismatch of the synchronized model. The 0.75 restraint coefficient imposes a conservative percentage-differential boundary during large through-current conditions. These values are fixed for every case so that the effect of R-SFCL resistance is not confounded by adaptive setting changes. They are study settings, not universal relay recommendations; field application requires coordination with CT class, charging-current compensation, communication performance, and the manufacturer’s characteristic [53],[55].

5. Fault Current Formulation

Symmetrical components are used to represent unbalanced faults because ABC, ABG, AB, and AG faults do not all excite the same sequence networks. Fortescue’s transformation decomposes phase quantities into positive, negative, and zero sequence components [44]. For an AG fault, the boundary conditions are

where  is the fault resistance in sequence form, the AG fault current satisfies

where , , and  are the positive, negative, and zero sequence fault currents.

If  and  are the positive sequence impedances from the fault point to terminals M and N, and  and  are the zero sequence impedances, the sequence fault current can be written as

where , , and  are the sequence voltages at the fault point, and ∥ denotes parallel impedance. Equation (14) shows that RSFCL changes the current distribution and therefore modifies the relay quantities.

The terminal current contribution from terminal M is represented by

while the terminal N contribution is

Here  is the pre fault line current. The positive and zero sequence current distribution factors are

The pre fault load current is estimated from

where  and  are the terminal voltages. These equations clarify how the  changes both the fault current and the terminal current balance used by the relay.

6. System Parameters and Measurement Settings

The simulated line uses the parameters summarized in Table 1. The two sources are rated at 230 kV and have phase angles of zero degrees and 20 degrees. The source resistance and inductance are included so that short circuit currents are not idealized. The 100 km line is represented using positive and zero sequence parameters, which are required for balanced and unbalanced fault studies [2].

Table 1. Transmission line and source parameters used in the simulation

The relay uses a 10 kHz sampling frequency and a one-cycle 50 Hz phasor-estimation window, corresponding to 200 samples per cycle. This sampling rate provides sufficient resolution for the transient response while supporting stable extraction of the fundamental current component. The source is represented by a balanced, grounded three-phase Thevenin equivalent. The same per-phase resistance and inductance are used for the positive-, negative-, and zero-sequence source networks, as listed in Table 1. Consequently, the results are most directly applicable to systems with comparable source sequence impedances; networks with substantially different zero-sequence source characteristics should be assessed using their measured parameters.

The maximum detectable fault resistance is obtained using the procedure in Figure 2. For each fault type and R-SFCL resistance, the fault resistance is increased until either (10) or (11) is no longer satisfied. The preceding value is retained as the sensitivity limit. Since each setting represents a deterministic simulation case, the protection benefit is expressed through absolute and percentage changes in the sensitivity limit and through the marginal gain between successive limiter resistances.

Figure 2. Flowchart used to calculate the maximum detectable fault resistance for each fault type and R-SFCL resistance

7. Relay Implementation and Practical Limitations

The relay processes one 20 ms cycle of current samples from each line terminal. At the 10 kHz sampling rate, this corresponds to 200 samples per terminal. These samples are used to estimate the 50 Hz current phasors, after which the differential current, restraint current, and trip decision are calculated directly from (7) to (11). The required processing is modest for a numerical relay because only two short sample windows and a small number of direct calculations are involved. The dominant operating delay is therefore the one-cycle measurement window rather than the calculation itself. Accordingly, the scheme is intended for dependable current differential protection and not for sub-millisecond travelling-wave protection.

Practical differential protection is sensitive to errors in terminal-current measurement and time alignment [53]. At 50 Hz, a synchronization error of 100 μs introduces about 1.8° phase displacement, while a 1 ms error introduces about 18° [54]. CT ratio error creates a proportional current mismatch, and CT saturation produces additional magnitude and phase distortion during heavy external faults [55]. Communication delay does not affect the comparison when both terminal measurements carry accurate timestamps and are aligned before calculation; unequal delay, packet loss, or incorrect timestamps can create a false differential quantity [56]. Practical implementation should therefore include CT-saturation supervision, suitable restraint during severe through faults, data-quality and packet-loss checks, and continuous monitoring of time synchronization [55]. The simulations assume correctly scaled CT signals and synchronized communication. The reported results therefore quantify internal-fault sensitivity for the stated model and settings; external-fault security under CT saturation, communication disturbances, and measurement noise requires separate validation.

8. Relay Principle and Network Diagrams

Figure 3 illustrates the operating principle of current differential protection. With terminal-current polarities directed into the protected zone, the corrected currents cancel during normal loading and external faults but add during an internal fault. Figure 4 shows the two-terminal transmission line, the location of the R-SFCL near terminal M, the terminal current measurements, and the internal fault point. Together, the diagrams define the protected zone and the measurement locations used in the simulation.

Figure 3. Current differential relay principle for the protected transmission line

Figure 4. Two terminal transmission line model with terminal sources, R-SFCL location, relay measurements, and internal fault point

3. RESULTS AND DISCUSSION

1. Sensitivity Improvement Under Different Fault Types

Table 2 summarizes the maximum detectable fault resistance for ABC, ABG, AB, and AG faults. The no-limiter reference is constant for each fault type because it is evaluated using the same line and relay settings. The R-SFCL case changes with limiter resistance because the post quench resistance modifies the terminal current distribution and the differential-restraint ratio.

The sensitivity gain depends on the selected limiter resistance (Table 3). At 5 Ω, the improvements are 3.8%, 5.2%, 3.1%, and 7.1% for ABC, ABG, AB, and AG faults, respectively. At 10 Ω, the gains increase to 7.7%, 9.1%, 9.2%, and 10.0%, and at 20 Ω they reach 15.4%, 15.6%, 12.3%, and 14.3%. The highest values within the investigated range are 15.4% for ABC, 19.5% for ABG, 12.3% for AB, and 18.6% for AG. These maxima are reached at 20 Ω for ABC and AB faults and at 30 Ω for ABG and AG faults. Thus, the final improvement for each fault type applies only after its corresponding threshold resistance has been reached.

Marginal gain was calculated from the change in the maximum detectable fault resistance between successive R-SFCL settings. For ABC and AB faults, no further increase in sensitivity occurs above 20 Ω. For ABG and AG faults, increasing the limiter from 20 to 30 Ω adds 3 Ω to the detectable fault-resistance limit, whereas the 30–50 Ω and 50–100 Ω increments produce no additional gain. Thus, every fault type reaches a nearly constant sensitivity level once the SFCL resistance reaches 30 Ω, indicating that further increases in resistance provide negligible additional improvement in protection sensitivity. Across the six investigated resistance settings, the average sensitivity enhancements are 12.18% for ABC faults, 14.72% for ABG faults, 10.26% for AB faults, and 14.52% for AG faults, with corresponding standard deviations of 5.11%, 6.18%, 3.73%, and 4.98%, respectively. The standard deviation quantifies the variability of the sensitivity improvement across the tested SFCL resistance values. A relatively small standard deviation indicates that the improvement remains consistent and stable over the investigated resistance range, whereas a larger standard deviation reflects a stronger dependence of relay sensitivity on the selected SFCL resistance. Therefore, the obtained standard deviations confirm that, despite minor variations among fault categories, the proposed protection scheme delivers a robust and repeatable enhancement in sensitivity, with the improvement becoming increasingly stable as the SFCL resistance approaches its optimal operating region.

Table 2. Maximum detectable fault resistance for all investigated internal faults.

Table 3. Percentage sensitivity improvement and marginal-gain interpretation across the complete R-SFCL sweep

Figure 5. Maximum detectable fault resistance as a function of equivalent R-SFCL resistance

2. Graphical Sensitivity Results

Figure 6 provides a waveform-based view of the relay sensitivity under low-impedance and high-resistance fault conditions. The first three cases, shown in Figure 6(a) to Figure 6(c), represent low-impedance ABC, AB, and AG faults, respectively. In these cases, the fault current is sufficiently high, and the relay operating quantity remains clearly distinguishable from the prefault condition. This indicates that low-impedance faults are not the most critical operating condition for the current differential relay, because the differential current can easily exceed the relay pickup setting. In Figure 6(a), the ABC low-impedance fault produces a balanced three-phase response. Since the fault involves all phases, the relay receives strong current contribution from both line terminals. This makes the internal fault condition easy to identify. Similarly, Figure 6(b) shows that the AB low-impedance fault still produces a clear disturbance in the affected phases, although the response is lower than the three-phase case because the zero-sequence path is not involved.

      In Figure 6(c), the AG fault response includes the ground-return path, and the waveform confirms that the relay remains sensitive to single-line-to-ground faults when the fault resistance is low. The last three cases in Figure 6(d) to Figure 6(f) show the more demanding ABC fault conditions with increasing fault resistance. When the fault resistance is increased to 20 ohms in Figure 6(d), the post-fault waveform is still clearly visible, and the relay has sufficient operating margin. However, as the resistance increases to 50 ohms in Figure 6(e), the post-fault current magnitude becomes smaller, and the fault signature becomes less pronounced. This reduction is expected because a higher fault resistance limits the fault current and weakens the differential quantity available to the relay. The most severe case is shown in Figure 6(f), where the ABC fault resistance is 100 ohms. In this case, the waveform amplitude is much closer to the pre-fault level, meaning that the relay operates near its sensitivity boundary. This is the region where the R-SFCL becomes most useful. The limiter does not simply reduce the current; it changes the current distribution between the two-line terminals and improves the differential-restraint relationship. Therefore, the graphical results in Figure 6 confirm the numerical sensitivity results reported in Table 2. The R-SFCL provides limited additional value when the fault is already easy to detect, but it becomes more valuable when the fault resistance increases and the relay approaches its operating boundary.

Figure 6. Grouped sensitivity plots for low impedance and high resistance fault cases

3. Fault Current Suppression Without and with R-SFCL

Figure 7 shows the time-domain fault current responses when the R-SFCL is not installed. In all four cases, the fault produces a sharp increase in current magnitude immediately after fault inception. The ABC fault in Figure 7(a) gives the highest current, reaching approximately 3750 A. This is expected because a three-phase fault is a balanced short-circuit condition and normally produces the largest current contribution from the source network. Such a high current level can impose severe electrodynamic and thermal stress on line conductors, current transformers, circuit breakers, and other primary equipment.

For the ABG fault shown in Figure 7(b), the peak current reaches approximately 3249 A. This value is lower than the ABC case but still severe because the fault includes both phase-to-phase and ground-return components. The AB fault in Figure 7(c) reaches approximately 3197 A. Since this fault does not involve the zero-sequence network, its current path differs from the ground fault cases, but the current magnitude remains high enough to stress protection and switching equipment. The AG fault in Figure 7(d) produces a lower peak current of approximately 2900 A, which is consistent with the additional impedance introduced by the ground-return path. The corresponding responses with the R-SFCL are shown in Figure 8. The effect of the limiter is immediately visible in all cases. In Figure 8(a), the ABC fault current is reduced from approximately 3750 A to 2200 A after limiting. This corresponds to a reduction of about 41.3%. The ABG response in Figure 8(b) decreases from 3249 A to 2183 A, giving a reduction of about 32.8%. In Figure 8(c), the AB fault current decreases from 3197 A to 2160 A, corresponding to a reduction of about 32.4%. For the AG fault in Figure 8(d), the current decreases from 2900 A to 2000 A, giving a reduction of about 31.0%.

Figure 7. Time domain fault current responses without the R-SFCL

Figure 8. Time domain fault current responses with the R-SFCL

These reductions are important because electrodynamic force increases approximately with the square of current, while thermal stress depends on the energy released during the fault. A reduction of at least 31% in peak current therefore lowers both mechanical and thermal duty before circuit-breaker interruption. Relay coordination was preserved: every reported internal-fault case satisfied the 200 A pickup and restraint conditions in (10) and (11) after limiting. The R-SFCL thus reduced fault-current stress without preventing identification of faults within the protected zone.

4. Comparative Relay Performance

Table 4 compares peak current, current reduction, maximum detectable fault resistance, sensitivity gain, and the minimum R-SFCL resistance required to reach the final sensitivity limit. ABC and AB faults reach their final limits at 20 Ω, whereas ABG and AG faults require 30 Ω. All reported operating points satisfy both (10) and (11), showing that current suppression and sensitivity improvement occur simultaneously.

Table 4. Summary of CDP relay performance with and without the R-SFCL

Comparison With Previous Studies and Engineering Implications

Previous studies have demonstrated that SFCLs can effectively reduce short-circuit currents in AC grids, DC systems, wind farms, electric aircraft systems, and HVDC networks [47]–[50], and recent work further confirms their relevance in modern networks with distributed generation and hybrid energy resources [51]. However, fault-current reduction alone is not sufficient to prove protection benefit, because an SFCL can also modify relay input quantities such as apparent impedance, sequence current, current magnitude, and supervising signals [24]–[26],[37]. Therefore, this study extends previous work by focusing specifically on current differential protection, where relay operation depends on the comparison of terminal currents rather than only local current magnitude or apparent impedance. The results show that the R-SFCL improves the maximum detectable fault resistance while reducing destructive fault-current levels, indicating better internal-fault sensitivity. A key practical finding is that the improvement saturates when the R-SFCL resistance reaches about 20–30 Ω, meaning that excessively high limiter resistance may add thermal burden, recovery stress, and transient voltage impact without providing further relay benefit.

4. CONCLUSION

This study investigated the use of a resistive-type superconducting fault current limiter to enhance transmission-line current differential protection. A MATLAB/Simulink-based protection model was developed to evaluate ABC, ABG, AB, and AG internal faults with and without the R-SFCL. The limiter reduced peak fault current while preserving relay dependability, as all reported internal-fault cases satisfied both the 200 A pickup condition and the 0.75 differential-restraint criterion after limiting. The maximum detectable fault resistance increased from 78 Ω to 90 Ω for ABC faults, 77 Ω to 92 Ω for ABG faults, 65 Ω to 73 Ω for AB faults, and 70 Ω to 83 Ω for AG faults. These changes correspond to sensitivity improvements of 15.4%, 19.5%, 12.3%, and 18.6%, respectively. The larger gains for ABG and AG faults reflect the influence of the limiter on the sequence-current distribution and the differential-restraint operating margin. The results also show that the protection benefit saturates when the R-SFCL resistance reaches approximately 20–30 Ω. This is an important practical finding because it indicates that increasing the limiter resistance beyond this range may not provide additional relay sensitivity improvement. Therefore, R-SFCL design should not be based only on maximizing fault-current reduction, but on coordinated selection of limiter resistance, relay pickup, and restraint settings. Hence, the study confirms that a properly coordinated R-SFCL can reduce equipment stress, improve high-resistance fault detection, and support more dependable current differential protection for transmission lines. The main limitation of this work is that the analysis is based on deterministic simulation using selected system parameters and relay settings. Practical factors such as current transformer saturation, communication delay, synchronization error, measurement noise, detailed R-SFCL thermal recovery, and hardware relay filtering were not fully modeled. Future work should therefore include real-time digital simulation, hardware-in-the-loop validation, external fault stress testing, CT saturation analysis, and coordinated optimization of R-SFCL resistance with practical relay settings.

DECLARATION

Acknowledgement

The authors acknowledge the Department of Electrical Engineering, King Fahd University of Petroleum and Minerals, Saudi Arabia, for academic support.

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